The present invention relates generally to digital circuits, and more particularly, to a configurable flip-flop circuit.
The complexity of integrated circuit (IC) design has continually increased over the years. As a result, using computer software to design an IC has become a necessity. Computer aided design (CAD) tools are used to create an IC blueprint, referred to as a layout, which illustrates a logic level design of the IC. To design the layout, a circuit design is simplified into various logic cells and then these logic cells are appropriately combined to generate a circuit that performs the function of the circuit design. A place-and-route CAD program is then used to optimize the circuit design. The place-and-route program re-arranges the logic cells and the corresponding interconnections to define the most suitable routing scheme and channels to connect the logic cells and other circuit elements. The place-and-route program has a library of predefined logic cell types (e.g., NOT, NAND, NOR, XOR, multiplexer, flip-flop, and other combinational logic circuits) to implement the circuit design.
Design is followed by fabrication, where the blueprint (layout) is used to create basic complementary metal-oxide-semiconductor (CMOS) transistor layers, contact and metal layers in silicon using a combination of semiconductor processes including depositing, masking, etching and so on. The CMOS transistor layers, and the contact and metal layers define the elements and interconnections of the IC and are combined to form a functional IC.
Certain modifications may be needed in the original layout to either delete or add logic elements and interconnections during the fabrication stage. To expedite the modification process, engineering change orders (ECOs) are generated to document the desired modifications. Thereafter, the layout is modified using the place-and-route CAD tool to incorporate the desired changes.
Conventional IC design protocols often provide additional spare logic cells of different types in the layout. These spare logic cells are used to implement the ECOs. However, due to limitations of the IC design software environment, only a predetermined number and types of spare logic cells are included in the layout, which limits the modifications that may be performed to implement the ECOs. Thus, desired functions may have to be removed or the layout process re-initiated with the desired logic cells. However, re-designing the IC and generating a new layout is very costly and time consuming.
Further, even if a desired spare logic cell is available in the layout, the position of the spare logic cell may not be suitable to meet routing and timing closure requirements. The IC designer is required to painstakingly identify alternate routing paths to circumvent the position constraints of the spare logic cells, thereby leading to higher turnaround time for incorporating the ECO.
Therefore, it would be advantageous to have a solution that provides a high degree of flexibility for implementing ECOs, and simplifies routing and timing closure requirements.